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Summary

In this chapter we briefly surveyed several approaches that employ customized and heterogeneous memory architectures and organizations, in order to achieve the desired performance or power budgets of specific application domains.

The trend of such customization, although commonly used for embedded, or domain specific architectures, will continue to influence the design of newer programmable embedded systems. System architects will need to decide which groups of memory accesses deserve decoupling from the computations, and customization of both the memory organization itself, as well as the software interface (e.g., ISA-level) modifications to support efficient memory behavior. This leads to the challenging tasks of decoupling critical memory accesses from the computations, scheduling such accesses (in parallel or pipelined) with the computations, and the allocation of customized (special-purpose) memory transfer and storage units to support the desired memory behavior. Typically such tasks have been performed by system designers in an ad-hoc manner, using intuition, previous experience, and limited simulation/exploration. Consequently many feasible and interesting memory architectures are not considered. In the following chapters we present a systematic strategy for exploration of this memory architecture space, giving the system designer improved confidence in the choice of early, memory architectural decisions.

Keywords

Digital Signal Processing File System Access Pattern Cache Line Memory Architecture 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Kluwer Academic Publishers 2002

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