Designing Power Analysis Resistant and High Performance Block Cipher Coprocessor Using WDDL and Wave-Pipelining

  • Yuanman Tong
  • Zhiying Wang
  • Kui Dai
  • Hongyi Lu
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4318)


Novel design method and design flow of block cipher coprocessor is presented based on the WDDL (Wave Dynamic Differential Logic) and Wave-Pipelining techniques. This design flow utilized the current commercially available EDA (Electronic Design Automatic) tools to a large degree. The WDDL and wave-pipelining based coprocessor not only resists power analysis, but also achieves high performance and low power consumption in nature. According to the design flow, this paper implements a DES coprocessor. The simulation results show that the novel design method does achieve high performance, low power consumption and power analysis resistant ability at the cost of chip area.


WDDL Wave-pipelining block cipher power analysis resistant design flow 


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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Yuanman Tong
    • 1
  • Zhiying Wang
    • 1
  • Kui Dai
    • 1
  • Hongyi Lu
    • 1
  1. 1.School of Computer ScienceNational University of Defense TechnologyChangsha, HunanP.R.C.

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