A Parallel Permutation Multiplier for a PGM Crypto-chip

  • Tamás Horváth
  • Spyros S. Magliveras
  • Tran van Trung
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 839)


A symmetric key cryptosystem, called PGM, based on logarithmic signatures for finite permutation groups was invented by S. Magliveras in the late 1970’s. PGM is intended to be used in cryptosystems with high data rates. This requires exploitation of the potential parallelism in composition of permutations. As a first step towards a full VLSI implementation, a parallel multiplier has been designed and implemented on an FPGA (Field Programmable Gate Array) chip. The chip works as a co-processor in a DSP system. This paper explains the principles of the architecture, reports about implementation details and concludes by giving an estimate of the expected performance in VLSI.


Field Programmable Gate Array Setup Phase Parallel Multiplier Potential Parallelism Logarithmic Signature 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 1994

Authors and Affiliations

  • Tamás Horváth
    • 1
  • Spyros S. Magliveras
    • 2
  • Tran van Trung
    • 1
  1. 1.Institute for Experimental MathematicsUniversity of EssenEssenGermany
  2. 2.Department of Computer Science and EngineeringUniversity of NebraskaLincolnUSA

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