Silicon Nanocrystal Nonvolatile Memory
Part of the Nanostructure Science and Technology book series (NST)
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Silicon nanocrystal memory devices , such as shown in Fig. 4.1, offer the potential to solve the challenging problem of scaling nonvolatile memories. Scaling of floating-gate (FG) nonvolatile memory cells has been limited to bottom oxide thicknesses in the range of 80–110 Å primarily because of the vulnerability to charge loss from the conducting FG through isolated defects in the tunnel oxide that arise after repeated write/erase operations. As a result the FG, operating voltages are in the range of 16–20 V required for erasing the memory cell by Fowler-Nordheim tunneling of carriers from the FG to the channel. This voltage is sometimes split as ±8 to ±10 V using fully isolated wells. Silicon nanocrystal memory cells that store charge in isolated centers inside a gate dielectric are less susceptible to charge loss through isolated defect paths in the tunnel oxide due to their discontinuous nature of charge storage. In other words, an underlying oxide defect leads to charge loss only from charge storage sites in its immediate proximity. Once the impact of defect-mediated charge loss is mitigated, charge loss is primarily due to tunneling and the tunnel oxide in these devices can be scaled down to about 50–60 Å based on retention-time requirements. The scaling of the tunnel oxide results in embedded memory modules that can operate with a maximum on-chip voltage of ±6 V, allowing reduction of the memory module size by up to a factor of 2 at the 90-nm technology node, as shown in Fig. 4.2 . Furthermore, this reduction in operating voltage enables sharing of logic I/O device implants with the high-voltage periphery devices, which are used to charge and discharge the memory bitcells in the array.
KeywordsGate Bias Silicon NANOCRYSTAL Memory Window Threshold Voltage Shift Charge Loss
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