• Andreas HanssonEmail author
  • Kees Goossens
Part of the Embedded Systems book series (EMSY)


Embedded systems are rapidly growing in numbers and importance as we crowd our living rooms with digital televisions, game consoles and set-top boxes and our pockets (or maybe handbags) with mobile phones, digital cameras and personal digital assistants. Even traditional PC and IT companies are making an effort to enter the consumer-electronics business [5] with a mobile phone market that is four times larger than the PC market (1.12 billion compared to 271 million PCs and laptops in 2007) [177].


Intellectual Property Design Flow Inverse Discrete Cosine Transform Very Long Instruction Word Clock Domain 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. [2]
    AHBLite (2001) Multi-Layer AHB, AHB-Lite Product Information. ARM Limited, San Jose, CAGoogle Scholar
  2. [4]
    Altera (2008) Avalon Interface Specifications. Altera Corporation, San Jose, CA. Available on Google Scholar
  3. [5]
    Anderson MR (2004) When companies collide: the convergence to consumer electronics. Strategic News Service, Friday Harbor, WAGoogle Scholar
  4. [6]
    ARINC653 (1997) ARINC Specification 653. Avionics Application Software Standard InterfaceGoogle Scholar
  5. [8]
    AXI (2003) AMBA AXI Protocol Specification. ARM Limited, San Jose, CAGoogle Scholar
  6. [9]
    Azimi M, Cherukuri N, Jayashima D, Kumar A, Kundu P, Park S, Schoinas I, Vaidya A (2007) Integration challenges and tradeoffs for tera-scale architectures. Intel Technology Journal 11(3):173–184CrossRefGoogle Scholar
  7. [12]
    Beigne E, Clermidy F, Vivet P, Clouard A, Renaudin M (2005) An asynchronous NOC architecture providing low latency service and its multi-level design framework. In: Proc. ASYNCGoogle Scholar
  8. [14]
    Bekooij M, Moreira O, Poplavko P, Mesman B, Pastrnak M, van Meerbergen J (2004) Predictable embedded multiprocessor system design. LNCS 3199:77–91Google Scholar
  9. [19]
    Benini L, de Micheli G (2002) Networks on chips: a new SoC paradigm. IEEE Computer 35(1):70–80CrossRefGoogle Scholar
  10. [21]
    van Berkel K (2009) Multi-core for mobile phones. In: Proc. DATEGoogle Scholar
  11. [27]
    Bjerregaard T, Sparsø J (2005) A scheduling discipline for latency and bandwidth guarantees in asynchronous network-on-chip. In: Proc. ASYNCGoogle Scholar
  12. [28]
    Bjerregaard T, Mahadevan S, Grøndahl Olsen R, Sparsø J (2005) An OCP compliant network adapter for GALS-based SoC design using the MANGO network-on-chip. In: Proc. SOCGoogle Scholar
  13. [29]
    Bjerregaard T, Stensgaard M, Sparsø J (2007) A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution method. In: Proc. DATEGoogle Scholar
  14. [33]
    Buttazo GC (1977) Hard Real-Time Computing Systems: Predictable Scheduling Algorithms and Applications. Kluwer Publishers, DordrecthGoogle Scholar
  15. [35]
    Carloni L, McMillan K, Sangiovanni-Vincentelli A (2001) Theory of latency-insensitive design. IEEE Transactions on CAD of Integrated Circuits and Systems 20(9):1059–1076CrossRefGoogle Scholar
  16. [43]
    Dally WJ, Towles B (2001) Route packets, not wires: on-chip interconnection networks. In: Proc. DACGoogle Scholar
  17. [46]
    Dielissen J, Rădulescu A, Goossens K, Rijpkema E (2003) Concepts and implementation of the Philips network-on-chip. In: IP-Based SOC DesignGoogle Scholar
  18. [49]
    DTL (2002) Device Transaction Level (DTL) Protocol Specification. Version 2.2. Philips Semiconductors, Washington, DCGoogle Scholar
  19. [50]
    Dutta S, Jensen R, Rieckmann A (2001) Viper: a multiprocessor SOC for advanced set-top box and digital TV systems. IEEE Design and Test of Computers 18(5):21–31CrossRefGoogle Scholar
  20. [51]
    Ernst D (2004) Limits to modularity: a review of the literature and evidence from chip design. Economics Study Area Working Papers 71, East-West Center, Honolulu, HIGoogle Scholar
  21. [54]
    FSL (2007) Fast Simplex Link (FSL) Bus v2.11a. Xilinx, Inc, San Jose, CAGoogle Scholar
  22. [55]
    Gal-On S (2008) Multicore benchmarks help match programming to processor architecture. In: MultiCore ExpoGoogle Scholar
  23. [62]
    Goossens K, Dielissen J, Gangwal OP, González Pestana S, Rădulescu A, Rijpkema E (2005) A design flow for application-specific networks on chip with guaranteed performance to accelerate SOC design and verification. In: Proc. DATEGoogle Scholar
  24. [63]
    Goossens K, Dielissen J, Rădulescu A (2005) The Æthereal network on chip: concepts, architectures, and implementations. IEEE Design and Test of Computers 22(5):21–31Google Scholar
  25. [64]
    Graham R (1969) Bounds on multiprocessing timing anomalies. SIAM Journal of Applied Mathematics 17(2):416–429zbMATHCrossRefGoogle Scholar
  26. [68]
    Hansson A, Goossens K (2007) Trade-offs in the configuration of a network on chip for multiple use-cases. In: Proc. NOCSGoogle Scholar
  27. [69]
    Hansson A, Goossens K (2009) An on-chip interconnect and protocol stack for multiple communication paradigms and programming models. In: Proc. CODES+ISSSGoogle Scholar
  28. [71]
    Hansson A, Coenen M, Goossens K (2007) Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip. In: Proc. CODES+ISSSGoogle Scholar
  29. [72]
    Hansson A, Coenen M, Goossens K (2007) Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip. In: Proc. DATEGoogle Scholar
  30. [74]
    Hansson A, Goossens K, Rădulescu A (2007) A unified approach to mapping and routing on a network on chip for both best-effort and guaranteed service traffic. VLSI Design 2007:1–16Google Scholar
  31. [75]
    Hansson A, Wiggers M, Moonen A, Goossens K, Bekooij M (2008) Applying dataflow analysis to dimension buffers for guaranteed performance in Networks on Chip. In: Proc. NOCSGoogle Scholar
  32. [77]
    Hansson A, Goossens K, Bekooij M, Huisken J (2009) Compsoc: a template for composable and predictable multi-processor system on chips. ACM Transactions on Design Automation of Electronic Systems 14(1):1–24CrossRefGoogle Scholar
  33. [78]
    Hansson A, Subburaman M, Goossens K (2009) Aelite: a flit-synchronous network on chip with composable and predictable services. In: Proc. DATEGoogle Scholar
  34. [79]
    Hansson A, Wiggers M, Moonen A, Goossens K, Bekooij M (2009) Enabling application-level performance guarantees in network-based systems on chip by applying dataflow analysis. IET Computers and Design TechniquesGoogle Scholar
  35. [80]
    Henkel J (2003) Closing the SoC design gap. Computer 36(9):119–121CrossRefGoogle Scholar
  36. [87]
    Ilitzky DA, Hoffman JD, Chun A, Esparza BP (2007) Architecture of the scalable communications core’s network on chip. IEEE Micro 27(5):62–74CrossRefGoogle Scholar
  37. [88]
    ITRS (2007) International technology roadmap for semiconductors. System DriversGoogle Scholar
  38. [89]
    ITRS (2007) International technology roadmap for semiconductors. DesignGoogle Scholar
  39. [90]
    Jantsch A (2006) Models of computation for networks on chip. In: Proc. ACSDGoogle Scholar
  40. [96]
    Keutzer K, Malik S, Newton AR, Rabaey JM, Sangiovanni-Vincentelli A (2000) System-level design: orthogonalization of concerns and platform-based design. IEEE Transactions on CAD of Integrated Circuits and Systems 19(12):1523–1543CrossRefGoogle Scholar
  41. [101]
    Kopetz H, El Salloum C, Huber B, Obermaisser R, Paukovits C (2008) Composability in the time-triggered system-on-chip architecture. In: Proc. SOCCGoogle Scholar
  42. [102]
    Kramer J, Magee J (1990) The evolving philosophers problem: dynamic change management. IEEE Transactions on Software Engineering 16(11):1293–1306, http://10.1109/32.60317CrossRefGoogle Scholar
  43. [103]
    Krstić M, Grass E, Gürkaynak F, Vivet P (2007) Globally asynchronous, locally synchronous circuits: overview and outlook. IEEE Design and Test of Computers 24(5):430–441CrossRefGoogle Scholar
  44. [109]
    Lickly B, Liu I, Kim S, D Patel H, Edwards SA, Lee EA (2008) Predictable programming on a precision timed architecture. In: Proc. CASESGoogle Scholar
  45. [111]
    Lu Z, Haukilahti R (2003) NOC application programming interfaces: high level communication primitives and operating system services for power management. In: Networks on Chip, Kluwer Academic Publishers, DordrechtGoogle Scholar
  46. [112]
    Magarshack P, Paulin PG (2003) System-on-chip beyond the nanometer wall. In: Proc. DACGoogle Scholar
  47. [115]
    Marescaux T, Mignolet J, Bartic A, Moffat W, Verkest D, Vernalde S, Lauwereins R (2003) Networks on chip as hardware components of an OS for reconfigurable systems. In: Proc. FPLGoogle Scholar
  48. [117]
    Martin G (2006) Overview of the MPSoC design challenge. In: Proc. DACGoogle Scholar
  49. [131]
    Moreira O, Valente F, Bekooij M (2007) Scheduling multiple independent hard-real-time jobs on a heterogeneous multiprocessor. In: Proc. EMSOFTGoogle Scholar
  50. [138]
    Murali S, Coenen M, Rădulescu A, Goossens K, De Micheli G (2006) A methodology for mapping multiple use-cases on to networks on chip. In: Proc. DATEGoogle Scholar
  51. [139]
    Muttersbach J, Villiger T, Fichtner W (2000) Practical design of globally-asynchronous locally-synchronous systems. In: Proc. ASYNCGoogle Scholar
  52. [140]
    Nachtergaele L, Catthoor F, Balasa F, Franssen F, De Greef E, Samsom H, De Man H (1995) Optimization of memory organization and hierarchy for decreased size and power in video and image processing systems. In: Proc. MTDTGoogle Scholar
  53. [141]
    Nachtergaele L, Moolenaar D, Vanhoof B, Catthoor F, De Man H (1998) System-level power optimization of video codecs on embedded cores: a systematic approach. Journal of VLSI Signal Processing 18(12):89–109Google Scholar
  54. [143]
    Nesbit K, Moreto M, Cazorla F, Ramirez A, Valero M, Smith J (2008) Multicore resource management. IEEE Micro 28(3):6–16CrossRefGoogle Scholar
  55. [144]
    Nieuwland A, Kang J, Gangwal O, Sethuraman R, Busá N, Goossens K, Peset Llopis R, Lippens P (2002) C-HEAP: a heterogeneous multi-processor architecture template and scalable and flexible protocol for the design of embedded signal processing systems. Design Automation for Embedded Systems 7(3):233–270zbMATHCrossRefGoogle Scholar
  56. [146]
    Obermaisser R (2007) Integrating automotive applications using overlay networks on top of a time-triggered protocol. LNCS 4888:187–206Google Scholar
  57. [147]
    OCP (2007) OCP Specification 2.2. OCP International PartnershipGoogle Scholar
  58. [152]
    Owens J, Dally W, Ho R, Jayasimha D, Keckler S, Peh LS (2007) Research challenges for on-chip interconnection networks. IEEE Micro 27(5):96–108CrossRefGoogle Scholar
  59. [154]
    Panades I, Greiner A, Sheibanyrad A (2006) A low cost network-on-chip with guaranteed service well suited to the GALS approach. In: Proc. NANONETGoogle Scholar
  60. [156]
    Paukovits C (2008) The time-triggered system-on-chip architecture. PhD thesis, Technische Universität Wien, Institut für Technische InformatikGoogle Scholar
  61. [160]
    PLB (2003) Processor Local Bus (PLB) v3.4. Xilinx Inc, San Jose, CAGoogle Scholar
  62. [161]
    Poplavko P, Basten T, Bekooij M, van Meerbergen J, Mesman B (2003) Task-level timing models for guaranteed performance in multiprocessor networks-on-chip. In: Proc. CASESGoogle Scholar
  63. [162]
    Pullini A, Angiolini F, Murali S, Atienza D, De Micheli G, Benini L (2007) Bringing NoCs to 65 nm. IEEE Micro 27(5):75–85CrossRefGoogle Scholar
  64. [165]
    Rostislav D, Vishnyakov V, Friedman E, Ginosar R (2005) An asynchronous router for multiple service levels networks on chip. In: Proc. ASYNCGoogle Scholar
  65. [166]
    Rowen C, Leibson S (2004) Engineering the Complex SOC: Fast, Flexible Design with Configurable Processors. Prentice Hall PTR, Upper Saddle River, NJGoogle Scholar
  66. [169]
    Rumpler B (2006) Complexity management for composable real-time systems. In: Proc. ISORCGoogle Scholar
  67. [172]
    Sasaki H (1996) Multimedia complex on a chip. In: Proc. ISSCCGoogle Scholar
  68. [173]
    Sgroi M, Sheets M, Mihal A, Keutzer K, Malik S, Rabaey J, Sangiovanni-Vincentelli A (2001) Addressing the system-on-a-chip interconnect woes through communication-based design. In: Proc. DACGoogle Scholar
  69. [177]
    Smith B (2008) ARM and Intel battle over the mobile chip’s future. Computer 41(5):15–18CrossRefGoogle Scholar
  70. [180]
    Soudris D, Zervas ND, Argyriou A, Dasygenis M, Tatas K, Goutis C, Thanailakis A (2000) Data-reuse and parallel embedded architectures for low-power, real-time multimedia applications. In: Proc. PATMOSGoogle Scholar
  71. [189]
    TechInsights (2008) Embedded Market Study, TechInsights, Ottawa ONGoogle Scholar
  72. [201]
    Wingard D (2004) Socket-based design using decoupled interconnects. In: Interconnect-Centric design for SoC and NoC, Kluwer, DordrechtGoogle Scholar
  73. [205]
    Zhang H (1995) Service disciplines for guaranteed performance service in packet-switching networks. Proceedings of the IEEE 83(10):1374–1396CrossRefGoogle Scholar
  74. [70]
    Hansson A, Goossens K, Rădulescu A (2005) A unified approach to constrained mapping and routing on network-on-chip architectures. In: Proc. CODES+ISSSGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  1. 1.Research & Development ARM Ltd.CambridgeUK
  2. 2.Eindhoven University of TechnologyEindhovenThe Netherlands

Personalised recommendations