Statistical MOS Model
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Advances in microelectronics fabrication coupled with the desire to create faster, more complex MOS circuits have pushed the feature size of many analog/digital VLSI processes to the 1–2 µm range. Because variances in parameters such as channel length, channel width, threshold voltage and substrate doping do not scale with dimension, relative device mismatch increases as the feature size is reduced. It is expected that performance variances, caused by this mismatch, in short-channel MOS circuits will be crucial and may, ultimately, introduce a limitation for device scaling in integrated circuits.
KeywordsParameter Correlation Parameter Mismatch Coordinate Method Circuit Layout Statistical Parameter Model
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