High-k Related Design Issues
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Analog and mixed-signal circuit design issues related to high-k are analyzed in Chap. 3. The impact of increased flicker noise and dynamic variations of threshold voltage are discussed exemplary. Flicker noise reduction techniques are briefly discussed. A systematic analysis of hysteresis effects in analog and mixed-signal circuits is provided for the first time. Switched capacitor amplifiers, comparator and A/D converter based on successive approximation (SAR-ADC) are identified as sensitive building blocks, tolerable levels for dynamic variations of threshold voltage are derived. Switched input comparators and non-binary A/D conversion are proposed as countermeasures to compensate for performance degradation of comparators and A/D converters. The implementation of a non-binary 12 bit SAR-ADC in high-k CMOS is shown, the efficiency of the error correction mechanism is verified on silicon.
KeywordsPhase Noise Hysteresis Effect Flicker Noise Charge Trapping Hysteresis Parameter
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