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High-k Related Design Issues

  • Michael FuldeEmail author
Chapter
  • 922 Downloads
Part of the Springer Series in Advanced Microelectronics book series (MICROELECTR., volume 28)

Abstract

Analog and mixed-signal circuit design issues related to high-k are analyzed in Chap. 3. The impact of increased flicker noise and dynamic variations of threshold voltage are discussed exemplary. Flicker noise reduction techniques are briefly discussed. A systematic analysis of hysteresis effects in analog and mixed-signal circuits is provided for the first time. Switched capacitor amplifiers, comparator and A/D converter based on successive approximation (SAR-ADC) are identified as sensitive building blocks, tolerable levels for dynamic variations of threshold voltage are derived. Switched input comparators and non-binary A/D conversion are proposed as countermeasures to compensate for performance degradation of comparators and A/D converters. The implementation of a non-binary 12 bit SAR-ADC in high-k CMOS is shown, the efficiency of the error correction mechanism is verified on silicon.

Keywords

Phase Noise Hysteresis Effect Flicker Noise Charge Trapping Hysteresis Parameter 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media B.V. 2010

Authors and Affiliations

  1. 1.Infineon Technologies Austria AGVillachAustria

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