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Models in Memory Testing

From Functional Testing to Defect-Based Testing
  • Stefano Di CarloEmail author
  • Paolo Prinetto
Chapter
  • 675 Downloads
Part of the Frontiers in Electronic Testing book series (FRET, volume 43)

Abstract

Semiconductor memories have been always used to push silicon technology at its limit. This makes these devices extremely sensible to physical defects and environmental influences that may severely compromise their correct behavior. Efficient and detailed testing procedures for memory devices are therefore mandatory. As physical examination of memory designs is too complex, working with models capable of precisely representing memory behaviors, architectures, and fault mechanisms while keeping the overall complexity under control is mandatory to guarantee high quality memory products and to reduce the overall test cost. This is even more important as we are fully entering the Very Deep Sub Micron era. This chapter provides an overview of models and notations currently used in memory testing practice highlighting challenging problems waiting for solutions.

Keywords

Memory testing Memory modeling Fault models March test 

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Copyright information

© Springer Science+Business Media B.V. 2010

Authors and Affiliations

  1. 1.Control and Computer Engineering DepartmentPolitecnico di TorinoTorinoItaly

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