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Physical Fault Models and Fault Tolerance

  • Jean ArlatEmail author
  • Yves Crouzet
Chapter
  • 662 Downloads
Part of the Frontiers in Electronic Testing book series (FRET, volume 43)

Abstract

Dependable systems are obtained by means of extensive testing procedures and the incorporation of fault tolerance mechanisms encompassing error detection (on-line testing) and system recovery. In that context, the characterization of fault models that are both tractable and representative of actual faults constitute an essential basis upon which one can efficiently verify, design or assess dependable systems. On one hand, models should refer to erroneous behaviors that are as abstract and as broad as possible to allow for the definition and development of both generic fault tolerance mechanisms and cost-effective injection techniques. On the other hand, the models should definitely aim at matching the erroneous behaviors induced by real faults.

In this chapter, we focus on the representativeness of fault models with respect to physical faults for deriving relevant testing procedures as well as detection mechanisms and experimental assessment techniques. We first discuss the accuracy of logic fault models with respect to physical defects in the implementation of off-line/on-line testing mechanisms. Then, we show how the fault models are linked to the identification and implementation of relevant fault injection-based dependability assessment techniques.

Keywords

Defect characterization Fault models Testability improvement Testing procedures Test sequences generation Layout rules Coding Error detection Self-checking Fault-injection-based testing Dependability assessment 

Notes

Acknowledgements

The pioneering research reported in Section 8.2 was led by Christian Landrault at LAAS-CNRS. Incidentally, it constitutes his first work on hardware testing, topic on which he has eagerly contributed since then at LIRMM. We are really pleased that we have been given the opportunity to participate in this way to this special book! The authors would like to thank several colleagues and friends from EFCIS (now ST Microelectronics), ESPRIT project PDCS, IST project DBench and from IFIP WG 10.4 on Dependable Computing and Fault Tolerance, for the fruitful exchanges along the years on the various topics addressed in the Chapter. In particular, we are grateful to Alain Costes and Michel Diaz (LAAS-CNRS), and also X. Messonnier, P. Rousseau, and Michel Vergniault (EFCIS) for their helpful comments, suggestions, and assistance for the study reported in Section 8.2. For what concerns Section 8.3, thanks go to Jean-Claude Laprie and Karama Kanoun (LAAS-CNRS), Johan Kalrsson and Peter Folkesson (Chalmers U.), Hermann Kopetz, Günther Leber and Emmerich Fuchs (Vienna UT), for their contributions to the reflections carried out and to the comprehensive comparative study reported. This work was supported in part by DRET, EFCIS, ESPRIT project PDCS, IST project DBench, and IST network of excellence ReSIST. Jacques Galiay, whose contribution to the work on offline testing was essential, sadly deceased in the early 1980s, during a hike in the Alps mountains.

References

  1. Aidemark JL, Vinter JP, Folkesson P, Karlsson J (2001) GOOFI: A generic fault injection tool. Proceedings of IEEE/IFIP DSN. Göteborg, Sweden, pp 83–88Google Scholar
  2. Arlat, J (1990) Dependability validation by fault injection: method, implementation, application, Doctorat d’Etat Dissertation, INP, Toulouse, France (In French, available from LAAS)Google Scholar
  3. Arlat J, Aguera M, Amat L, Crouzet Y, Fabre J-C, Laprie J-C, Martins E, Powell D (1990) Fault injection for dependability validation – a methodology and some applications. IEEE TSE 16(2):166–182Google Scholar
  4. Arlat J, Crouzet Y (2002) Faultload representativeness for dependability benchmarking. Suppl. Volume IEEE/IFIP DSN. Washington, DC, USA, pp F.29–F.30Google Scholar
  5. Arlat J, Crouzet Y, Karlsson J, Folkesson P, Fuchs E, Leber GH (2003) Comparison of physical and software-implemented fault injection techniques. IEEE TC 52(9):1115–1133Google Scholar
  6. Avižienis A, Laprie J-C, Randell B, Landwehr C (2004) Basic concepts and taxonomy of dependable and secure computing. IEEE TDSC 1(1):11–33Google Scholar
  7. Baumann R (2005) Soft errors in advanced computer systems. IEEE Des Test Comput 22(3): 258–266CrossRefGoogle Scholar
  8. Benso A, Prinetto P (eds) (2003) Fault injection techniques and tools for embedded systems reliability evaluation. Frontiers in electronic testing, 23. Kluwer Academic, London, UK, 245p.Google Scholar
  9. Bouricius WG, Carter WC, Schneider PR (1969) Reliability modeling techniques for self-repairing computer systems. Proceedings of the 24th ACM National Conference, pp 295–309Google Scholar
  10. Crouzet Y, Landrault C (1980) Design of self-checking LSI circuits – application to a 4-bit microprocessor. IEEE TC C-29(6):532–537Google Scholar
  11. Crouzet Y (1978) Design of self-checking large scale integration circuits Ph.D Dissertation, INP, Toulouse, France (in French, available from LAAS)Google Scholar
  12. Crouzet Y, Galiay J, Landrault C, Rousseau P Vergniault M (1978) Definition and design of easily testable or self-testing LSI circuits Contract Rep. DRET 77/008, LAAS Report 1787, 334 p (in French)Google Scholar
  13. Crouzet Y, Waeselynck H, Lussier B, Powell D (2006) The SESAME experience: from assembly languages to declarative models. Proceedings of Mutation 2006, Raleigh, NC, USAGoogle Scholar
  14. Daran M, Thévenod-Fosse P (1996) Software error analysis: a real case study involving real faults and mutations. Proceedings of ISSTA’96, San Diego, CA, USA, 1996, pp 158–171Google Scholar
  15. de Andrés D, Ruiz JC, Gil D, Gil P (2008) Fault emulation for dependability evaluation of VLSI systems. IEEE TVLSIS 16(4):422–431Google Scholar
  16. Durães J, Madeira H (2006) Emulation of software faults: a field data study and a practical approach. IEEE TSE 32(11):849–867Google Scholar
  17. Folkesson PS, Svensson S, Karlsson J (1998) A comparison of simulation based and scan chain implemented fault injection. Proceedings of FTCS. Munich, Germany, pp 284–293Google Scholar
  18. Fuchs E (1996) An evaluation of the error detection mechanisms in MARS using software-implemented fault injection. Proceedings of EDCC. Taormina, Italy, pp 73–90Google Scholar
  19. Galiay J (1978) Design of easily testable LSI circuits PhD Dissertation, UPS, Toulouse, France (in French, available from LAAS)Google Scholar
  20. Galiay J, Crouzet Y, Vergniault M (1980) Physical versus logical faults models in MOS-LSI circuits – impact on their testability. IEEE TC C-29(6):527–531Google Scholar
  21. Gil P, Arlat J, Madeira H, Crouzet Y, Jarboui T, Kanoun K, Marteau T, Durães J, Vieira M, Gil D, Baraza JC, Gracia J (2002) Fault representativeness. IST Project DBench, Deliverable ETIE2, 101p.. Available at www.laas.fr/dbench/deliverables.html
  22. Hély D, Bancel F, Flottes M-L, Rouzeyre B (2005) Scan design and security: can they work together? Sophia Antipolis MicroElectronics, Sophia Antipolis, FranceGoogle Scholar
  23. Johansson R (1994) On single event upset error manifestation. Proceedings of EDCC. Berlin, Germany, pp 217–231Google Scholar
  24. Kanoun K, Spainhower L (Eds) (2008) Dependability benchmarking for computer systems. IEEE CS Press and Wiley, 362 p.,Google Scholar
  25. Kopetz H, Bauer G (2003) The time-triggered architecture. Proceedings of IEEE 91(1):112–126CrossRefGoogle Scholar
  26. Kopetz H, Holzer P, Leber G, Schindler M (1991) The rolling ball on MARS. Vienna University of Technology, Research Report, No 13/91Google Scholar
  27. Leveugle R (2007) Early analysis of fault-based attack effects in secure circuits. IEEE TC 56(10):1431–1434MathSciNetGoogle Scholar
  28. Moraes R, Barbosa R, Durães J, Mendes N, Martins E, Madeira H (2006) Injection of faults at component interfaces and inside the component code: are they equivalent? Proceedings of EDCC. Coimbra, Portugal, pp 53–64Google Scholar
  29. Powell D (1994) Distributed fault-tolerance – lessons from Delta-4. IEEE Micro 14(1):36–47CrossRefGoogle Scholar
  30. Reisinger J, Steininger A, Leber G (1995) The PDCS implementation of MARS hardware and software. In Predictably dependable computing systems, pp 209–224Google Scholar
  31. Rennels DA, Avižienis A, Ercegovac M (1978) A study of standard building blocks for the design of fault-tolerant distributed computer systems Proceedings of IEEE FTCS Toulouse, France, pp 144–149Google Scholar
  32. Roth JP, Bouricius WG Schneider PR (1978) Programmed algorithms to compute tests to detect and distinguish between failures in logic circuits IEEE TC C-16(10):567–580Google Scholar
  33. Sedmak RS Liebergot HL (1978) Fault-tolerance of a general purpose computer implemented by very large scale integration Proceedings of FTCS Toulouse, France, pp 137–143Google Scholar
  34. Stott DT, Ries G, Hsueh M-C, Iyer RK (1998) Dependability analysis of a high-speed network using software-implemented fault injection and simulated fault injection. IEEE TC 47(1): 108–119Google Scholar
  35. Wadsack RL (1978) Fault modelling and logic simulation of CMOS and MOS integrated circuits Bell Syst Tech J 57:1449–1473zbMATHGoogle Scholar

Copyright information

© Springer Science+Business Media B.V. 2010

Authors and Affiliations

  1. 1.LAAS-CNRS; Université de ToulouseToulouseFrance

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