• Frank RoginEmail author
  • Rolf Drechsler


Modern integrated circuits and systems consist of many different functional blocks comprising multiple heterogeneous processor cores, dedicated analog/mixed signal components, various on-chip busses and memories, (third-party) Intellectual Property (IP), and most notably more and more embedded software. Following “Moore’s Law”, the available chip capacity grows exponentially. Currently, high-end processor designs reaches up to 2 billion transistors. A complete system can be integrated onto a single chip which is then called System-on-a-Chip (SoC). The increasing design complexity and scale of SoC designs combined with non-functional requirements and constraints on the final product, e.g. low power, robustness, reliability, and low cost, make the verification of the design correctness a complex and crucial task. Functional errors are still the most important cause of design respins. According to a study from Collett International Research [Cir04] nearly 40% of all chip designs require at least one re-spin. There, 75% of these designs contain functional or logical bugs. The increasing amount of embedded software implemented in integrated circuits further complicates verification. Studies, e.g. [Hum04], implicate that software still contains about 10 to 20 defects per 1,000 lines of code after compiling and testing is done. Remarkably, software companies have to spend nearly the same cost and time efforts on quality assurance like hardware manufacturers have to invest [Tas02].


  1. Cir04.
    Collett International Research. IC/ASIC Functional Verification Study, 2002/2004.Google Scholar
  2. Hum04.
    W. S. Humphrey. The quality attitude. In news@sei 2004 | Number 3, [Online], accessed May 2008.
  3. Tas02.
    G. Tassey. The Economic Impacts of Inadequate Infrastructure for Software Testing. National Institute for Standards and Technology, 2002.Google Scholar
  4. Fos06.
    C. Eibl, C. Albrecht, and R Hagenau. gSysC: A Graphical Front End for SystemC. In European Conference on Modelling and Simulation, pp. 257–262, 2005.Google Scholar
  5. OSCI.
    OSCI. SystemC home page. [Online], accessed July 2008.
  6. GDPG01.
    A. Gerstlauer, R. Dömer, J. Peng, and D.D. Gajski. System Design - A Practical Guide with SpecC. Springer, 2001.Google Scholar
  7. RF04.
    F. Rogin and E. Fehlauer. FSM-Based Rule Specification Aiming at a Generic Code Analysis Library. In Work-in-Progess Session at EUROMICRO, 2004.Google Scholar
  8. RFSH05.
    F. Rogin, E. Fehlauer, A. Schneider, and J. Haase. Automatische Generierung von Dokumentationen für VHDL-AMS-Modellbibliotheken. In ASIM Workshop, 2005, Slides [Online], Scholar
  9. RFHO07.
    F. Rogin, E. Fehlauer, C. Haufe, and S. Ohnewald. Debug Patterns for Efficient High-level SystemC Debugging. In IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, pp. 403–408, 2007.Google Scholar
  10. RF+07.
    F. Rogin, E. Fehlauer, S. Rülke, S. Ohnewald, and T. Berndt. Non-Intrusive High-level SystemC Debugging. In Advances in Design and Specification Languages for Embedded Systems, pp. 131–144, Springer, July 2007.CrossRefGoogle Scholar
  11. RGDR08.
    F. Rogin, C. Genz, R. Drechsler, and S. Rülke. An Integrated SystemC Debugging Environment. In Embedded Systems Specification and Design Languages: Selected papers from FDL 2007, pp. 59–71, Springer, 2008.CrossRefGoogle Scholar
  12. RK+08.
    F. Rogin, T. Klotz, G. Fey, R. Drechsler, and S. Rülke. Automatic Generation of Complex Properties for Hardware Designs. In Design, Automation, and Test in Europe, pp. 545–548, 2008.Google Scholar
  13. RK+09.
    F. Rogin, T. Klotz, G. Fey, R. Drechsler, and S. Rülke. Advanced Verification by Automatic Property Generation. IET Computers & Digital Techniques, 3(4):338–353, 2009.CrossRefGoogle Scholar
  14. RDR09.
    F. Rogin, R. Drechsler, and Steffen Rülke. Automatic Debugging of Systemon-a-Chip Designs. In IEEE International SOC Conference, pp. 333–336, 2009.Google Scholar

Copyright information

© Springer Science+Business Media B.V. 2010

Authors and Affiliations

  1. 1.Institutsteil EntwurfsautomatisierungFraunhofer - Institut für Integrierte SchaltungenDresdenGermany
  2. 2.Universität Bremen AG RechnerarchitekturBremenGermany

Personalised recommendations